EE 2381 Digital Computer Logic - Spring 2007

Digital computers and information; combinational logic circuits; combinational logic design; sequential circuits including finite-state machines; registers and counters; memory and programmed logic design. Design and simulation of digital computer logic circuits are studied. Concurrent registration in EE 2181.

Course Handouts [PDF format]

Course Syllabus Hex Arithmetic Karnaugh Maps - 3 Karnaugh Maps - 4
Digital Design, Mano Lecture 05 Supplement Lecture 06 Supplement Lecture 07 Supplement
Lecture 09 Supplement Lecture 10 Supplement Lecture 15 Supplement Lecture 22 Supplement
Lecture 26 Supplement      

Homework Assignments [PDF format]

Homework #01 Revised Homework #02 Homework #03 Revised Homework #04
Homework #05 Homework #06 Homework #07 Homework #08
Homework #09 Homework #10 Homework #11 Homework #12

Homework Solutions [PDF format]

Homework #01 Homework #02 Homework #03 Homework #04
Review Session I Exam I Homework #05 Homework #06
Homework #07 Homework #08 Review Session II Exam II
Homework #09 Homework #10 Homework #11 Homework #12
Final Review Session I Final Review Session II    

Lectures [PDF format]

Lecture #01 Lecture #02 Lecture #03 Lecture #04
Lecture #05 Lecture #06 Lecture #07 Lecture #08
Lecture #09 Lecture #10 Lecture #11 Midterm I
Lecture #13 Lecture #14 Lecture #15 Lecture #16
Lecture #17 Lecture #18 Lecture #19 Lecture #20
Midterm II Lecture #22 Lecture #23 Lecture #24
Lecture #25 Lecture #26 Lecture #27 Lecture #28

Topics [PDF format]

Topic #01 Topic #02 Topic #03 Topic #04
Topic #05 Topic #06 Topic #07 Topic #08
Topic #09 Topic #10 Topic #11 Topic #12
Topic #13 Topic #14 Topic #15 Topic #16
Topic #17 Topic #18 Topic #19 Topic #20
Topic #21 Topic #22 Topic #23 Topic #24
Topic #25 Topic #26 Topic #27 Topic #28
Topic #29 Topic #30 Topic #31 Topic #32
Topic #33 Topic #34 Topic #35 Topic #36

Verilog Downloads [Zip format]

Verilog Tutorial Examples Binary Adders D-Latch Dataflow Modeling and UDPs
Flip-Flop Models Counter Design Flip-Flop Timing Diagram Moore & Mealy
FSM Example #1 FSM Example #2 False Output Verilog & FSMs
Basic Shift Register